Magnetic bubble memories are now well known in the art. One mode of operation of such memories is termed the "field-access" mode because bubble movement in a film of bubble material is responsive to a magnetic drive field rotating in the plane of the film. Typically, the film comprises an epitaxial film of garnet although the use of amorphous films is contemplated. The bubble pattern, and thus stored bits of data represented by that pattern, move in the film along paths defined by a periodic pattern of magnetically soft (high permeability) elements, typically permalloy. The elements produce magnetic pole patterns that change as the drive field reorients to produce the localized field gradients for effecting bubble movement in the film.
The field-access, bubble memory is usually arranged in a "major-minor" organization disclosed in U.S. Pat. No. 3,618,054 of P. I. Bonyhard, U. F. Gianola, and A. J. Perneski issued Nov. 2, 1971. In that type of organization, the pattern of permalloy propagate elements defines a plurality of permanent storage loops, termed "minor" loops, in which bubble patterns are recirculated as the drive field reorients. Access to and from the minor loops is provided by means of an accessing channel or loop termed the "major" channel or loop also defined by permalloy elements. Bits are moved to and from the major loop at data exchange positions where the major and minor loops come into close proximity. In prior art bubble memories, the permalloy pattern defining the exchange positions operates, for example, to transfer or replicate data.
The major loop or channel of a bubble memory organized in the major-minor manner includes a data write and a data read position. If a major loop is employed, data is transferred to the accessing loop at the exchange positions leaving a vacancy in each minor loop. If the numbers of stages in the major and minor loops are chosen properly, data can be read out and (that data or updated data) returned to exchange positions in time to be transferred back into those vacancies during a single recirculation of the data about the loop. If a major channel is employed, an image of the stored data is replicated into the major channel for eventual annihilation after read out. There is in this latter case, of course, no necessity to return the data to the originating address, a procedure requiring a sufficient time for a complete recirculation of data about the minor loop. Thus, consecutive read operations can occur without the necessity of delay for data return in the latter organization. On the other hand, if a write operation is required, data annihilation is required along with a complete recirculation of the resulting vacancies, before the write operation is completed, in the latter organization also.
A figure of merit for the operation of various organizations for bubble memories is the "write cycle time" (or "read-rewrite" cycle time) which is the number of cycles of the drive field which occurs between consecutive write (or between read and subsequent rewrite) operations. For a major-minor organization having a single major channel for accessing, the average write cycle time is m/2 + m = 1.5m where m = the number of stages in a minor loop. It is typical in these types of memories that the number of minor loops is about equal to one-fourth the number of stages in a minor loop. The 1.5m figure occurs because in each instance, an address is selected and advanced to exchange positions (m/2 cycles on the average), and new data is advanced for transfer to the selected address when that address next appears at the exchange positions (m cycles).
An organization which exhibits improved write cycle time is one in which write and read operations are not performed in a single accessing channel but in separate accessing channels conveniently at opposite ends of the minor loops. In such double major channel bubble memories, on the average, m/2 cycles of the drive field are required to move an address to the exchange positions at the read accessing channel, and m/2 cycles are subsequently required to move the address to the exchange positions at the write channel, a total of m cycles in all.
It is a common operation in information systems to update data stored in a selected address. Frequently, the operation necessitates the comparison of stored data with tag bits to ascertain whether or not update is appropriate. The decision to update, in many systems, is delayed until read out occurs. That is to say, in many systems a decision to update data in a selected address is delayed until after the data stored in that address is read out. Particularly, in systems in which update decisions are delayed, a penalty is paid in write cycle time. In accordance with the present invention, no penalty need be paid in such systems.